The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2001

Filed:

Mar. 27, 1998
Applicant:
Inventors:

James Clark Baker, Crystal Lake, IL (US);

John Paul Oliver, Chicago, IL (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J 3/06 ;
U.S. Cl.
CPC ...
H04J 3/06 ;
Abstract

According to the present disclosure, an parallel formatted data signal is applied to an input (,), and the data signal is divided into a first data signal and a second data signal. The second data signal is applied to a logic delay element (,) to produce a delayed second data signal that is a delayed-in-time version of the first data signal. The first data signal is applied to a first parallel-to-serial converter (,), the delayed second signal is applied to a second parallel-to-serial converter (,), and first and second bit-serial data streams are produced. A controller (,) synchronizes an Arithmetic Logic Unit (,) to the first and second bit-serial data streams so that the ALU (,) scales and sums the first and second bit-serial data streams to produce a bit-serial, sample-rate converted, output signal.


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