The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 23, 2001
Filed:
Apr. 15, 1999
Kurt Pang, Fremont, CA (US);
Other;
Abstract
A method for forming gas pockets within integrated circuit devices to provide dielectric isolation between selected conductive structures in the integrated circuit device. The method is useable with many known integrated circuit manufacturing processes wherein the resulting device comprises, preferably, an uppermost layer of intermetal dielectric, on which the method of the present invention may be performed. In general, the method of the invention comprises the following steps. Providing an integrated circuit device structure with a top layer at least partly formed of a segregated conductive material and a solid dielectric material. Forming a mask over the top layer. Forming openings in the mask corresponding to positions where gas pockets are desired in the finished integrated circuit device. Etching through the openings in the mask to form gaps in the dielectric material of the top layer. Depositing a layer of dielectric material over the top layer to close the openings of the gaps formed in the dielectric material to create gas pockets or chambers in desired locations between conductive structures in the integrated circuit device.