Synchronization of branch cache searches and allocation/modification/deletion of branch cache

Abstract

A cache used with a pipelined processor includes an instruction cache, instruction buffers for receiving instruction sub-blocks from the instruction cache and providing instructions to the pipelined processor, and a branch cache. The branch cache includes an instruction buffer adjunct for storing an information set for each sub-block resident in the instruction buffers. A branch cache directory stores instruction buffer addresses corresponding to current entries in the instruction buffer adjunct, and a target address RAM stores target addresses developed from prior searches of the branch cache. A delay pipe, constituting serially-coupled registers, is used to step an information set read from the buffer instruction adjunct in synchronism with a transfer instruction traversing the pipeline. A comparison, at a predetermined phase along the delay pipe, determines if the information set identifies, as currently resident in the instruction buffers, a target address that matches the target address in the transfer instruction traversing the pipeline. If there is a finding that the information set did identify a target address in the instruction buffers that matches the target address in the transfer instruction traversing the pipeline and there is a TRA-GO from the pipeline, the instruction identified by the target address is sent to the pipeline from the instruction buffers rather than from the instruction cache.