The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2001
Filed:
Feb. 02, 1998
Nippon Telegraph and Telephone Corporation, Tokyo, JP;
Abstract
A scheme for carrying out modular calculations which is capable of carrying out modular calculations using redundant binary calculation even when a number of bits of the mantissa (dividend) is larger than a number of bits of the modulus (divisor). In this scheme, the divisor c in the divisor register is left shifted by (i−j) digits when a number of digits j of the divisor c is less than a number of digits i that can be stored in the divisor register, and the modular reduction a mod c is calculated up to (i−j)-th decimal place using the dividend a and the left shifted divisor c. Alternatively, the divisor c given in h-ary notation in the divisor register is left shifted by (i−j) digits when a number of digits j of the divisor c is less than a number of digits i that can be stored in the divisor register, while the dividend a given in h-ary notation in the dividend register is left shifted by (k−l) digits when a number of digits l of the dividend a is less than a number of digits k that can be stored in the dividend register, where k≧i. Then, the modular reduction a mod c is calculated up to a digit of [(k−l)−(i−j)]-th power of h using the left shifted dividend a and the left shifted divisor c to obtain a remainder, and this remainder is right shifted by (k−l) digits.