The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2001

Filed:

Apr. 26, 1999
Applicant:
Inventors:

Junya Taniguchi, Tokyo, JP;

Yasuji Koshikawa, Tokyo, JP;

Kouji Mine, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 8/00 ;
Abstract

According to one disclosed embodiment, a synchronous semiconductor storage device (,) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (,) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (,). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK′ in a test mode. The ICLK′ signal can be applied to internal circuits (,) allowing such circuits to operate at a higher speed. The ICLK′ signal is not applied to the mode register setting circuit (,), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit,).


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