Merged memory and logic (mml) integrated circuit devices including buffer memory and methods of detecting errors therein

Abstract

An MML integrated circuit device includes a memory block, a logic circuit and a buffer memory, and a selection circuit that is coupled between the logic circuit and the buffer memory. The first selection portion is responsive to external data and to the logic circuit, to transmit external data or data from the logic circuit to the memory block via the buffer memory. Thus, MML integrated circuit devices can use the buffer memory to access the memory block during a normal operational mode and during a test mode. MML integrated circuit devices also preferably include a data expansion portion that is coupled between the external data and the selection portion, to replicate the external data a predetermined number of times and to transmit the replicated external data to the selection portion. Errors may be detected in an MML integrated circuit device that includes a memory block, a logic circuit and a buffer memory, by storing external data from external of the MML integrated circuit device into the buffer memory, and storing the external data from the buffer memory into the memory block. The external data is read from the memory block and the read external data is stored from the memory block into the buffer memory. The read external data is output from the buffer memory to external of the MML integrated circuit device. The external data may be stored from external of the MML integrated circuit device into the buffer memory by applying external data from external of the MML integrated circuit device to the MML integrated circuit device, replicating the external data a predetermined number of times in the MML integrated circuit device and storing the replicated external data in the buffer memory.