The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2001
Filed:
Mar. 11, 1999
T. J. Tseng, Hsinchu, TW;
David C. H. Cheng, Taoyuan Hsien, TW;
World Wiser Electronics Inc., Taoyuan Hsien, TW;
Abstract
A thermal vias-provided cavity-down IC package structure of the invention is provided. The thermal vias-provided cavity-down IC package structure includes a substrate, a heat sink and an adhesive layer for attaching the substrate to the heat sink. The substrate is formed of multiple layers of printed circuit boards which are attached to each other, and have a cavity formed at the center thereof. A plurality of thermal vias is formed surrounding the substrate. The head sink is divided into a chip mount area and a thermal via joint area. The chip mount area is used for a chip mount pad to be disposed thereon, wherein a chip is connected to the heat sink through the chip mount pad. The thermal via area is electrically coupled to the thermal vias thereby to form an approximate short path or a short path. Thus, heat energy is transferred not only by the heat sink directly, but also from the heat sink to the substrate through the thermal vias. Furthermore, since the depth of the chip mount area is adjustable, it is unnecessary to additionally grind the chip, resulting in a great saving of time and cost.