The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2001
Filed:
Jan. 29, 1999
Trenor F. Goodell, Peaks Island, ME (US);
Fairchild Semiconductor Corp., South Portland, ME (US);
Abstract
A logic level converter for translating CMOS logic signals to into differential logic signal pairs such as those associated with ECL levels. The converter includes a first converter branch coupled to the switchable CMOS level input and it provides a first switchable translated output. A second converter branch is not coupled to the input nor is it coupled to the first converter branch. The second converter branch provides a fixed reference signal output around which the output of the first converter branch switches. Changes in the input signal to the first converter branch cause its output potential to be more than or less than the potential of the fixed reference signal supplied by the second converter branch. The components of the respective branches may be tailored to position the fixed signal at a selectable level and to define the differential between the two output signals. The current associated with the converter is mirrored through both branches to minimize the effects of fabrication, temperature, and/or power supply vagaries.