The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2001
Filed:
Jun. 25, 1998
Nathaniel W. Bowe, Colchester, VT (US);
Ronald D. Rossi, Swanton, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method has been found to check contact to chips having inputs lacking a diode to substrate, such as silicon on insulator (SOI) chips. A mid level voltage, such as Vdd/2, is applied to each receiver sequentially to partially turn on both complementary devices of a CMOS inverter receiver or to partially turn on a current switch receiver. The overall chip standby leakage current is measured while a receiver is at the mid level voltage. These measurements are compared to the overall chip standby leakage current in normal operation when a logical high or logical low level is applied to all I/O pads. A mid level voltage is enough to partially turn on both complementary devices of an inverter receiver or to partially turn on a current switch receiver and the current going through that one receiver is sufficient to provide a significant increase in the overall chip standby current. Thus by measuring an overall chip Idd current, probe contact is checked for each receiver pad individually without directly accessing a current at each receiver pad.