Semiconductor chip having fieldless array with salicide gates and methods for making same

Abstract

A semiconductor process, which creates a semiconductor devices that includes logic transistors fabricated in a first region and a fieldless array fabricated in a second region, is provided. Both the logic transistors and the fieldless array transistors have gates comprising a polysilicon layer with a silicide layer. The logic transistors have self-aligned silicide regions formed on their source and drain regions. Self-aligned silicide regions are not formed on the source and drain regions of the fieldless array transistors, thereby preventing undesirable electrical shorts which could otherwise occur within the fieldless array. The silicide structures can be fabricated by depositing polysilicon over the first and second regions, etching the polysilicon layer in the first region to define gates of the logic transistors, depositing and reacting a refractory metal, removing the non-reacted refractory metal, and then patterning the polysilicon and silicide in the second region to define gates of the fieldless array transistors.