Division by iteration employing subtraction and conditional source selection of a prior difference or a left shifted remainder

Abstract

A data processing apparatus iteratively forms quotient, includes data registers (,) for storing various initial and intermediate quantities, a multiplexer (,) for selecting data from one of two data registers, a barrel rotator (,) and an arithmetic logic unit (,). A first register (,) stores the numerator, which is left shifted each iteration. A second register (,) stores the difference formed by the prior trial subtractions. A status register (,) set by the prior arithmetic logic unit (,) result controls the selection made by the multiplexer (,). A barrel rotator (,) rotates the data selected by multiplexer (,). The arithmetic logic unit (,) subtracts the divisor from the rotated quantity this result controls the iterative division process. If the difference is less than zero, then the rotated data is selected and the quotient bit is “0”. Otherwise, the prior difference is selected and the quotient bit is “1”. In the preferred embodiment, the numerator is split between two registers. The trial difference involves only the most significant bits of the numerator. In the preferred embodiment, the inverse of the divisor is stored and the difference is formed by adding the inverse of the divisor. The division processing repeats until the quotient is completely formed and loop logic controls the number of iterations. Also, the data processing apparatus is embodied as at least one digital image/graphics processor (,) as a part of a multiprocessor (,) formed in a single integrated circuit.