The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2001
Filed:
Apr. 06, 1998
Bradley W. Bartilson, Houston, TX (US);
Silicon Graphics, Inc., Mountain View, CA (US);
Abstract
An apparatus for electrically connecting a plurality chips to a circuit board includes a pair of ceramic chip carriers that have flexible circuits connected to the electrical contact locations on each ceramic chip. The apparatus for electrically connecting a plurality chips to a circuit board may also include an area between two chip connect surfaces which has multiple metallization layers isolated from one another by flexible isolation material. A flexible circuit extends beyond the edge of the ceramic chip or the chip-connect area and forms a flap. The flexible circuit flap includes electrical paths to pads on the chip-connect area of the device. Each flap portion of the flexible circuit has a set of pads. The pads on the flaps of the first and second ceramic chips are positioned to connect to a third set of pads on a printed circuit board. The printed circuit board is provided with pads positioned so that the pads on the flaps will correspond to the pads on the flaps of the ceramic chips. The circuit board is positioned near the edge of the first ceramic substrate and the second ceramic substrate so that the flaps of the first and second flexible circuit contact the third set of pads on said circuit board. The first and second ceramic chips having flexible circuit flaps or the device with the metallized layers isolated by flexible nonconductive material, can be stacked on one another to provide a very densely packaged unit. If cooling is a concern, thermally conducting surfaces can also be stacked with the devices. The thermally conductive surfaces can be heat pipes or surface treatments on the flat surface of the chip which conduct heat away from the components.