The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2001
Filed:
Dec. 18, 1997
David Chiang, Saratoga, CA (US);
Jesse H. Jenkins, IV, Danville, CA (US);
Robert A. Olah, Palo Alto, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method of operating a pin of an in-system programmable logic device (ISPLD) which includes the steps of (1) applying a predetermined voltage to the pin when the ISPLD is in a set-up mode, and (2) maintaining the last voltage applied to the pin when the ISPLD is in a normal operating mode. The ISPLD is in the set-up mode when the logic of the ISPLD has not yet been configured, or is being configured. The ISPLD is in the normal operating mode after the logic of the ISPLD has been configured. A particular ISPLD includes a pin and a logic gate having a first input terminal coupled to the pin, a second input terminal coupled to receive a control signal, and an output terminal coupled to the pin. When the ISPLD is in the set-up mode, the control signal causes the logic gate to apply a predetermined voltage to the pin. When the ISPLD is in the normal operating mode, the control signal causes the logic gate to maintain the last applied voltage on the pin.