Method of minimizing power use in programmable logic devices

Abstract

A method of minimizing power use in programmable logic devices (PLD) using programmable connections and scrap logic to create a versatile power management scheme. Individual product terms in a PLD can be powered off, thereby saving power, without incurring the power-up and settling time delays seen in the prior art. Power management is not restricted to any one function block, nor must the entire device be powered down, unless so programmed. All conventional logic functionality present in the PLD is available to the power management elements, allowing, in one embodiment, a standard function block to be programmed to operate as the control function block. This logic functionality includes, but is not limited to, internal feedback, combinatorial functions, and register functions. Because scrap logic resources left over from user programming and small programmable connections are used, minimal additional chip surface area is needed. No specific input/output pins are required; in fact, no external connections are required at all, though one or more may be used as inputs to the control function block logic. In some embodiments, power management can be accomplished using internal, on-chip signals alone. The pin-locking capabilities (compatibility) of conventional PLD designs are not affected and all function blocks remain identical, preserving maximum design flexibility for users.