The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2001

Filed:

Apr. 01, 1999
Applicant:
Inventors:

Duck-Hyung Lee, Kyoungki-do, KR;

Jong-Woo Park, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/170 ;
U.S. Cl.
CPC ...
H01L 2/170 ;
Abstract

Conductive lines are formed in integrated circuit memories using a Silicide blocking layer that is self-aligned. The Silicide blocking layer is self-aligned by etching an electrically insulating layer that is formed between a electrically conductive lines on a substrate in an integrated circuit memory. The etching removes the electrically insulating layer from the outer surfaces of the electrically conductive lines, but leaves a portion of the electrically insulating layer on the substrate between the electrically conductive lines. The portion of the electrically insulating layer remaining on the substrate may prevent the formation of a Silicide film on the substrate during a heating step used to form contacts on the outer surfaces of the electrically conductive lines. The self-aligned Silicide blocking layer may allow a reduction in the number of steps in the fabrication of the contacts and reduce the need to align a mask to the substrate to form the Silicide blocking layer.


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