Superscalar processor employing a high performance write back buffer controlled by a state machine to reduce write cycles

Abstract

A microprocessor of a superscalar structure having a datapath, a data cache, a bus unit and first and second pipelines includes a write buffer equipped in the bus unit and a write back buffer in the data cache to reduce write cycles. The write buffer receives data of a burst write cycle from the write back buffer and data of a single write cycle from the datapath. The write buffer in the microprocessor allows data to be written in the write buffer and then to be written in the external memory when the microprocessor is available for performing an external cycle. The processor includes a state machine to control the write buffer and also includes one write buffer for each of the first and second pipelines in order to diminish the write cycles. The write buffers also include a bit block which indicates whether information in the write buffer is written by a cache miss or a hit in a line having a shared state. The state machine includes idle, request, service, backoff (BOFF) and update states in controlling write cycle progression in a pipeline.