The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2001

Filed:

Jun. 18, 1999
Applicant:
Inventors:

Jung-Jen Liu, San Jose, CA (US);

Scott Smyers, San Jose, CA (US);

Bruce A. Fairman, Woodside, CA (US);

Steve Pham, Milpitas, CA (US);

Jose L. Diaz, San Jose, CA (US);

Richard A. Bardini, Los Gatos, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/334 ;
U.S. Cl.
CPC ...
G06F 1/334 ;
Abstract

A system and method for multi-level context switching in an electronic network comprises a control state machine configured to implement a data priority scheme, a return address generator configured to hold and release return addresses for interrupted instruction modules in accordance with the data priority scheme and context information from the electronic network, and a processor configured to process data from the electronic network in accordance with the data priority scheme and the context information. Receive registers stores data received from the electronic network. The control state machine includes a switch address generator and a program counter select. The switch address generator outputs a switch address, which is an address for a first instruction for a selected-context instruction module. The return address generator holds and releases the return addresses, which are addresses of next consecutive instructions, when an instruction module is interrupted for a context switch. The program counter select outputs a switch address, a return address, or a next consecutive address to select the appropriate instruction in the memory for execution by the processor.


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