The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2001
Filed:
Dec. 30, 1997
Ross Teggatz, McKinney, TX (US);
David J. Baldwin, Allen, TX (US);
Rex M. Teggatz, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An integrated circuit having a protected output field effect transistor (FET) (,). A drain-gate clamp circuit (,) is coupled to divert charge from the power FET drain electrode to the power FET gate electrode when excessive drain-source voltage is present. A drain-source current limit circuit (,) is coupled to divert charge from the power FET gate electrode to the power FET source electrode when a preselected drain-source current is achieved. A current limit inhibit circuit (,) is coupled between the current limit circuit and the power FET gate electrode, and having a control electrode coupled to the drain-gate clamp circuit. The current limit inhibit circuit (,) disables the current limit circuit (,) when charge flows in the drain-gate clamp circuit (,).