Semiconductor integrated circuit device with built-in timing regulator for output signals

Abstract

A semiconductor integrated circuit device is expected to output a multi-bit output signal at an extremely narrow timing in response to a system clock, wherein the semiconductor integrated circuit device includes synchronous latch circuits, a first phase-locked loop responsive to the system clock for producing a dummy data signal and a high-frequency intermediate clock signal, a delay circuit for producing a delayed clock signal delayed from the system clock by a predetermined number of clock pulses of the high-frequency intermediate clock signal and a second phase-locked loop comparing a dummy output signal with the delayed clock signal for producing a synchronous clock signal at appropriate timing, and the synchronous latch circuits is responsive to the synchronous clock signal for latching data signals and the dummy data signal, thereby outputting the output signals and the dummy output signal within the narrow timing.