The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2001

Filed:

Aug. 02, 1999
Applicant:
Inventor:

Douglas Robert Farrenkopf, Campbell, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 4/06 ;
U.S. Cl.
CPC ...
H03K 4/06 ;
Abstract

A method and circuit which employs negative feedback to generate a ramped voltage having well controlled maximum amplitude. In preferred embodiments, the invention is an integrated circuit (or portion of an integrated circuit) which generates a ramped voltage with controlled maximum amplitude in a manner independent of process and temperature variations in implementing and operating the circuit. Preferably, the circuit includes an amplifier having an input coupled to receive a reference signal, an output coupled to ramped voltage generator, and another input coupled to the output of the ramped voltage generator, thus implementing a negative feedback loop in which the amplifier asserts feedback to control the maximum amplitude of the ramped voltage generated by the ramped voltage generator. Preferably, the ramped voltage generator periodically charges and discharges a capacitor to generate the ramped voltage, the amplifier is a transconductance amplifier which is periodically enabled (for a portion of each charging cycle of the capacitor) in response to a clock signal, a one-shot circuit produces a delayed voltage pulse train in response to the clock signal, and the ramped voltage generator receives the delayed voltage pulse train and discharges the capacitor in response to each pulse of the delayed voltage pulse train.


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