Method for fabricating dram cell capacitor

Abstract

A DRAM cell capacitor and fabricating method thereof are provided, which can prevent the falling-down of a storage node. A storage node is formed by a first, second, and third conductive layer by sequentially forming a first conductive layer, a material layer having an etching selectivity with respect to the first conductive layer, and the second conductive layer, patterning the second conductive layer and the material layer by using a mask for forming a storage node, forming a third conductive layer on the first conductive layer including a second conductive layer pattern and a material layer pattern, and etching back the third conductive layer and the first conductive layer thereunder to form a poly-spacer, thereby decreasing the thickness of a storage node polysilicon layer with the height of an existing storage node, that is, cell capacitance being maintained and reducing the process throughput as well as minimizing the total etch amount of a polysilicon layer for forming a storage node during formation thereof, reducing the over-etch amount thereof, and preventing the falling-down of the storage node generated by an over-etch and subsequent cleaning process despite the misalignment of the storage node.