The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2001
Filed:
Jan. 23, 1998
Norikazu Itoh, Kyoto, JP;
Shunji Nakata, Kyoto, JP;
Yukio Shakuda, Kyoto, JP;
Masayuki Sonobe, Kyoto, JP;
Tsuyoshi Tsutsui, Kyoto, JP;
Rohm Co., Ltd., Kyoto, JP;
Abstract
Disclosed is a method of manufacturing a semiconductor light emitting device. Semiconductor overlying layers are formed on a substrate in a state of a wafer so that a light emitting area is provided therein. The semiconductor overlying layers includes first and second conductivity type layers. Part of the semiconductor overlying layers including the first conductivity type layer on a surface thereof is removed so as to expose part of the second conductivity type layer. Electrodes are formed, for each chip, respectively in connection with the surface of the first conductivity type layer and the surface of the exposed second conductivity type layer. The wafer is divided into individual chips. The exposed areas of the second conductivity type semiconductor layer is provided only part of a peripheral area of the chip so that the first conductivity type semiconductor layer is directly separated during dividing the wafer into individual chips. With such a method, when dividing a wafer into chips, the inefficiency of the space (etched areas do not contribute to light emission) is eliminated in etch-removing the semiconductor overlying layers at areas to be divided, thereby improving chip yield and hence reducing cost.