The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2000
Filed:
Jan. 26, 1999
Chun Jiang, San Jose, CA (US);
Wei Long, Sunnyvale, CA (US);
Zicheng G Ling, Sunnyvale, CA (US);
Yowjuang W Liu, San Jose, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
The invention provides a method and apparatus for calculating gate length and source/drain gate overlap, by measuring gate capacitance. The invention uses previously known fringe capacitance C.sub.fr and unit capacitance C.sub.OX. The invention measures gate capacitance C.sub.g, when the gate is accumulatively biased, and solves for overlap capacitance C.sub.OV using the equation C.sub.OV =(C.sub.g -2C.sub.fr)/2 or C.sub.OV =(C.sub.gg -C.sub.gb -2C.sub.fr)/2. The invention then measures the gate capacitance C.sub.g when the gate to source/drain voltage is set to inversion bias and a zero voltage is applied between the source/drain and the substrate, and solves for the channel capacitance C.sub.ch using the equation C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV. The invention calculates the channel capacitance C.sub.ch where C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV and then calculates gate length where gate length L.sub.g =(2C.sub.OV +C.sub.ch)/C.sub.OX and the effective gate length L.sub.eff =C.sub.ch /C.sub.OX. The invention further calculates source/drain gate overlap L.sub.OV, by setting L.sub.OV =C.sub.OV /C.sub.OX.