The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2000
Filed:
Aug. 28, 1998
John Miller, Rocklin, CA (US);
Richard Ortiz, Roseville, CA (US);
Chenmin Zhang, Fort Collins, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A method and a system for testing integrated devices such as chips used on a printed circuit board. The system includes test logic formed on the chip and coupled to bi-directional input/output pads. The system is capable of testing input pads, output pads, and bi-directional pads by coupling an input test signal from one pad of a pair of pads to the output of a second pad of the pair of pads. If the signal read out of the second pad corresponds to the expected value, the pads may be considered properly connected. The chips may be tested at any stage during chip manufacture, including after forming the die on a wafer, after cutting the die from the wafer and after packaging the die to produce the chip, and after attaching the chip to a printed circuit board. The system and method allow for quick and easy testing of pad connectivity during the manufacturing process, while minimizing the number of extra gates and trace lines on the chip.