Computer system ue recovery logic

Abstract

A computer system having central processors (CPs), an associated L2 cache, and processor memory arrays (PMAs), is provided with store logic and and fetch logic used to detect and correct data errors and to write the resulting data the associated cache. The store logic and and fetch logic blocks UEs from the cache for CP stores, for PMA (mainstore) fetches/loads, and for cache-to-cache loads, and with uncorrectable error recovery cache fetch and store logic injects `Special UEs` into the cache when loads cannot be blocked and abends CP jobs for UEs during CP stores, for UEs from PMA, for UEs from remote cache, and for UEs from local cache. This logic performs reconfiguring of memory when UEs are detected in memory and also blocks cache data propagation on UEs for CP fetches, for Cache-to-Cache transfer if data is unchanged, and for PMA castouts if data is unchanged, as well as forces castouts when UEs appear on changed cache data; injects `Special UEs` for UEs detected on changed cache data; invalidates the cache when UEs are detected in the local cache; and only deletes cache entries that have repeated failures.