State dependent synchronization circuit which synchronizes leading and

Abstract

A state dependent synchronization circuit synchronizes an asynchronous input signal to a clock signal to generate a synchronous output signal. The circuit synchronizes both the leading edge and the trailing edge of the input signal and also maintains the state of the output signal at a level corresponding to the input signal when the input signal does not change. The circuit includes an input signal latch which receives the input signal and provides a latched signal which does not charge state even if the input signal subsequently changes state until the latched signal is synchronized to the clock signal. The circuit further includes a synchronizer which synchronizes the latched signal with the clock signal. The synchronizer provides feedback signals to the input signal latch to permit the input signal latch to recognize a change in the state of the input signal only after the synchronizer has synchronized the previous state of the input signal. The synchronizer preferably includes a first stage and a second stage. The first stage of the synchronizer isolates the second stage from any oscillation which may occur if the latched signal changes state too close to a transition in the clock signal. The first stage and the second stage of the synchronizer preferably operate on opposite edges of the clock signal. The circuit preferably includes a pair of cross-coupled gates that enable the circuit to recognize and synchrinize pulses of very short duration.