Linearizing structures and methods for unity-gain folding amplifiers

Abstract

Linearized unity-gain folding amplifiers include first and second differential pairs of transistors that have offset voltages between control terminals and first current terminals. The control terminals are differentially coupled through input paths to a differential input port and the joined first current terminals receive respective first and second currents through respective first and second level-shift resistors. Thus, folded and level-shifted signals can be differentially coupled via output paths between the first and second level-shift resistors and an output port. For each of the differential pairs, at least one correction voltage is generated to substantially match the offset voltage of one of the transistors of that differential pair when a differential input voltage has one polarity and the offset voltage of another of the transistors when the differential input voltage has a different polarity. The correction voltage is inserted in one of the input paths in a feedback mode of the invention and in one of the output paths in a feed-forward mode and the correction voltage is oriented to correct variations in the offset voltages of one of the differential pairs that occur adjacent a polarity transition of the differential input voltage. In serial arrangements of these amplifiers, their high linearity enhances the quantization processes of successive stages so that longer serial arrangements can be reliably used.