The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2000
Filed:
Dec. 23, 1998
Applicant:
Inventors:
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B / ; H03K / ;
U.S. Cl.
CPC ...
327108 ; 327112 ; 327111 ; 327109 ;
Abstract
An output buffer includes an NAND circuit, a first N channel MOS transistor connected between a power supply node and an output node, a second N channel MOS transistor connected between the output node and a ground node, the first to third drive circuits, and a delay circuit. The power supply voltage is first supplied to the gate of the second N channel MOS transistor by the second drive circuit. After a delay time delayed by the delay circuit has passed, boosted voltage is supplied to the gate of the second N channel MOS transistor by the third drive circuit. Accordingly, the output buffer is not influenced by the ringing and the pull-down characteristic improves.