The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2000
Filed:
Dec. 14, 1998
Motoko Tanaka, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A semiconductor integrated circuit device selectively decreasing the parasitic capacitance between wiring lines of a wiring layer is provided. This device is comprised of a semiconductor substructure with a main surface, an insulating layer formed on the main surface of the substructure, a first patterned conductive layer formed on the insulating layer to serve as a first-level wiring layer, and an interlevel dielectric layer formed on the insulating layer to cover the first-level wiring layer. The first-level wiring layer includes a first plurality of wiring lines and a second plurality of wiring lines. The first plurality of wiring lines are located apart from each other at gaps equal to or smaller than a specific value. The second plurality of wiring lines are located apart from each other at gaps larger than the specific value. The interlevel dielectric layer includes voids selectively located in the gaps of the first plurality of wiring lines, thereby decreasing a parasitic capacitance between the first plurality of wiring lines. The tops of the voids are lower than the tops of the first-level wiring layer, respectively.