Pipelined central processor incorporating indicator busy sensing and

Abstract

A pipelined processor for simultaneously performs one of a plurality of successive operations on each of a plurality of successive instructions within the pipeline, the successive operations including at least an instruction fetch stage, an operand address stage, an operand fetch stage, an execution stage and a result handling stage. The processor also maintains a plurality of indicators which are selectively updated during the result handling stage for a given instruction to reflect the results obtained during the execution stage thereof. When the second instruction of first and second successively fetched instructions is a conditional transfer, a determination is made as to which indicators may be affected by the execution of the first instruction, and a determination is also made as to which indicator the conditional transfer is to test to decide whether there is a GO or a NOGO condition. If the indicator to be tested by the conditional transfer instruction is among those which may be affected by the immediately preceding instruction, the conditional transfer instruction is held at a predetermined stage, for example, in operand addressing, in the pipeline for a predetermined period, such as one full clock cycle, to permit the indicator to be tested to settle before the conditional transfer instruction tests it.