Network interface device architecture for storing transmit and receive

Abstract

A network interface device includes a random access transmit buffer and a random access receive buffer for transmission and reception of transmission and receive data frames between a host computer bus and a packet switched network. The network interface device includes a memory management unit having read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memories between the read and write controllers. The synchronization circuit asynchronously monitors the amount of data stored in the random access transmit and receive buffer by asynchronously comparing write pointer and read pointer values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. A descriptor management unit is used to control DMA reading and writing of transmit data and receive data from and to system memory, respectively, based on descriptor lists, respectively. A pipelining architecture also optimizes transfer of data between the buffers, the PCI bus, and the media access controller.