Phase-locked loop (pll) circuit containing a frequency detector for

Abstract

An extended frequency lock range is achieved in a phase-locked loop (PLL) circuit based on sampled phase detectors by introducing frequency feedback into the PLL circuit. At least one data sampler samples adjacent bits of incoming data, such as data bits D.sub.X and D.sub.Y, and an edge detector samples an edge, E, of the incoming data signal between the two data bits, D.sub.X and D.sub.Y. Sequence values '101' or '010' for the data bits D.sub.X, E and D.sub.Y, are not valid and indicate that the VCO is sampling the incoming data stream too slowly. When sequence values of '101' or '010' are measured by the sampled phase detectors, the frequency of the VCO output, V.sub.O, is known to be too low, and a constant current is preferably injected by the sampled phase detector into the PLL, until the frequency becomes too high, upon which a constant current of opposite polarity is applied. A PLL circuit having a frequency detector in combination with a biased phase detector is also disclosed, to ensure that the PLL can be locked. A biased phase detector applies more phase error correction in one direction than in the other direction. For example, a positive biased phase detector applies more positive current, I.sub.UP, over time than negative current, I.sub.DOWN. The VCO control voltage is initialized to a value below the lock-in voltage for a positive biased phase detector embodiment, and the positive biased phase detector will cause a steady increase in the VCO control voltage until the PLL locks, thereby causing the phase error to be approximately zero.