The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2000

Filed:

Feb. 26, 1998
Applicant:
Inventors:

Gary A Brown, Fremont, CA (US);

Jitendra Mohan, Palo Alto, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B / ;
U.S. Cl.
CPC ...
375254 ; 375257 ; 375377 ; 333 19 ; 333177 ; 333178 ;
Abstract

A calibration circuit adjusts a differential output voltage from a line driver circuit when the differential output voltage falls outside a specified tolerance range. The calibration circuit includes a sample and hold circuit which samples the differential output voltage and holds a representative signal. A comparator compares the held signal with a reference voltage signal. When the held signal is greater than the reference voltage signal the comparator outputs a LOW signal and when the held signal is less than the reference voltage signal the comparator outputs a HIGH signal. The comparator output signal is stored in a memory circuit of a control logic. The control logic instructs an up/down counter to increment when the comparator output is LOW and to decrement when the comparator output is HIGH. A calibration current source sinks a unit of calibration current when the comparator output is LOW and sources a unit of calibration current when the comparator output is HIGH. The calibration current is added to an input current to calibrate the differential output voltage towards the specified tolerance range. In a next cycle of the calibration sequence, if a new comparator output signal is different from that stored in the memory circuit, the calibration sequence ceases. However, if the new comparator output signal is the same as that stored in the memory circuit the calibration sequence continues.


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