Semiconductor memory with auto-tracking bit line precharge scheme

Abstract

Disclosed herein is a semiconductor memory device which comprises a decoding block, an OR gate and first and second precharge circuits. The decoding block generates section word line select signals and column select signals in response to a block select signal and row and column pre-decoder signals. And, the OR gate mixes the section word line select signals to generate a precharge signal. This forces the first precharge circuit to be activated or inactivated in synchronization with the section word line select signals. Furthermore, the second precharge circuit is activated or inactivated in synchronization with the column select signals. According to the precharge scheme of the present invention, there is prevented the period of the inactivation (activation) of the top and bottom precharge signals from being overlapped with the period of the activation (inactivation) of the section word line. As a result, the semiconductor memory device has an improved access speed.