The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2000

Filed:

Jul. 14, 1999
Applicant:
Inventors:

Min-Chul Chung, Ansan, KR;

Kyeong-Rae Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518905 ; 36518911 ; 365205 ;
Abstract

The semiconductor memory device includes a memory cell array, sense amplifying means for generating a sense output signal pair, and a data output buffer for providing the sense output signal pair. The data output buffer includes a level shifter for generating a first data output signal pair by shifting the level of the sense output signal pair responsive to the output buffer enable signal. A register inverts and latches the first data output signal pair, generating a second data output signal pair. A first transmission and latch means transmits and latches the second data output signal pair generating a third data output signal pair responsive to a first control signal. A second transmission and latch means transmits and latches the second data output signal pair generating a fourth data output signal pair responsive to a second control signal. A first inverter generates a fifth data output signal pair by inverting the third data output signal pair responsive to a first data output control signal. A second inverter generates the fifth data output signal pair by inverting the fourth data output signal pair responsive to a second data output control signal. A first latch generates a sixth data output signal pair by latching the fifth data output signal pair. A logical multiplication means manipulates the sixth data output signal pair responsive to an output enable signal.


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