The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2000
Filed:
Jan. 14, 1999
James L Burnham, Morgan Hill, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method and circuit is provided for creating multiple product lines from a single silicon implementation of an integrated circuit (IC). Specifically, logic blocks within the IC are selectively disabled after manufacturing the IC to create various ICs of different functionality from a single silicon implementation of the IC. In one embodiment, a first logic block of the IC is coupled to a disable circuit by a first disable line and a second logic block of the IC is coupled to the disable circuit by a second disable line. The disable circuit can disable the first logic block by driving the first disable line to a disable logic state. Similarly, the disable circuit can disable the second logic block by driving the second disable circuit to the disable logic state. In an FPGA embodiment of the present invention, the first logic block is a row of configurable logic blocks (CLBs) and the second logic block is a column of CLBs.