The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2000
Filed:
Jul. 17, 1998
Makoto Wakasugi, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
An interpolation circuit for calculating the value of an arbitrary point by interpolation using the values of points on the boundaries of a domain which surrounds the arbitrary point comprises a partial product generation circuit composed of multiplexers and a partial product addition circuit for adding partial products generated by the partial product generation circuit together. When an interpolated value f(C) between f(Ci) and f(Ci+1) (where the integer part of C is Ci and the decimal part of C as a binary number of n digits is c=C.sub.n-1 2.sup.n-1 +C.sub.n-2 2.sup.n-2 + . . . +C.sub.1 2.sup.1 +C.sub.0 2.sup.0) is calculated by the interpolation circuit, each multiplexer MPk+1 (k=0, 1, . . . , n-2, n-1) corresponding to 2.sup.k of the decimal part c is supplied with two input values f(Ci) and f(Ci+1) and one selection signal Ck (k=0, 1, . . . , n-2, n-1) respectively and outputs f(Ci) or f(Ci+1) depending on the selection signal Ck, and the interpolated value f(C) is obtained by the partial product addition circuit by adding the outputs of the multiplexers MPk+1 (k=0, 1, . . . , n-2, n-1) corresponding to 2.sup.k as the partial products together. By use of the multiplexers as the partial product generation circuit, circuit composition of the interpolation circuit can be considerably simplified, and thus high speed interpolation calculation can be realized and systems which employ interpolation circuits can be miniaturized.