The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2000
Filed:
Jan. 04, 1999
James P Pequignot, Essex Junction, VT (US);
Tariq Rahman, Burlington, VT (US);
Jeffrey H Sloan, Burlington, VT (US);
Douglas W Stout, Milton, VT (US);
Steven H Voldman, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A novel ESD protection circuit for multiple power supplies, having both inventive inter-rail ESD circuitry and inventive single-rail ESD circuitry. The inter-rail ESD circuitry is scaleable and comprises one or more diode strings for interconnecting a pair of power rails. The ESD trigger voltage for a diode string is set by the number of diodes within the diode string and preferably a sufficient number of diodes are provided within each diode string for power-up and power-down sequence independence. The single-rail ESD circuitry is connected to a level-shifter and may comprise an RC discriminator comprising two NFET transistors connected in series. The RC discriminator may be connected to a clamping transistor via a buffering circuit, such as an inverter stage, that isolates the gate capacitance of the clamping transistor from the RC discriminator so that the RC characteristics of the RC discriminator are unaffected by the choice of the clamping transistor. The ESD protection circuit may be constructed from a selection from user-selectable discrete circuit elements formed on the chip.