Reduced skew control block clock distribution network

Abstract

A control block clock distribution network includes a logic circuit, one or more nth-level buffers, and a (n-1)th-level buffer that drives the one or more nth-level buffers. The logic circuit includes a predefined area containing substantially only clocked logic elements. The number of clocked logic elements in the predefined area is constrained to be less than or equal to a predetermined maximum number. The one or more nth-level buffers are located within the predefined area, whereas the (n-1)th-level buffer is located outside of the predefined area. Each nth-level buffer receives the clock signal outputted by the (n-1)th-level buffer and provides a clock signal to a predetermined number of the clocked logic elements within the predefined area Because the predefined area has known dimensions, the length of the clock line from the (n-1)th buffer to the nth-level buffers is known to within a range. Additionally, the number of clocked logic elements and the number of nth-level buffers are known to within a range. Thus, the range of resistive-capacitive loading to each clocked element within the predefined area is known. Accordingly, the maximum clock skew between clocked logic elements within the predefined area can be determined. The maximum clock skew of the predefined area can be adjusted to a desired value by varying one or more of the dimensions of the predefined area, the range of nth-level buffers that can be placed in the predefined area, or the range of clocked logic elements that can be driven by each nth-level buffer.