Local clock generator

Abstract

A local clock system for generating a local clock signal whose frequency and phase are synchronized to the frequency and phase of an external input clock reference signal, wherein the output local clock signal is a non-integer multiple of the input clock reference signal. A numerically controlled generator generates the clock output signal, and the frequency and phase thereof are controlled by a digital tuning word input thereto. An input frequency divider divides the input clock reference signal by a first constant k.sub.11 or a second constant k.sub.22, and an output frequency divider for dividing the output signal by a first constant k.sub.11 or a second constant k.sub.21. A relay-phase detector receives output signals from the input frequency divider and the output frequency divider, and produces a 0 or a 1 output, which controls the input frequency divider to divide by k.sub.12 or k.sub.22 and controls the output frequency divider to divide by k.sub.11 or k.sub.21, causing the input frequency divider and the output frequency divider to shift from one set of constants k.sub.12 and k.sub.11 to the second set of constants k.sub.22 and k.sub.21 upon a change in state of the output signal of the relay-phase detector. A phase accumulator is coupled to the output of the relay-phase detector, for detecting the accumulated phase output of the relay-phase detector, and the output thereof controls the numerically controlled signal generator.