The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2000
Filed:
Dec. 18, 1998
Applicant:
Inventor:
Edward S McGettigan, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
326 39 ; 326 38 ; 326 39 ;
Abstract
In an FPGA having four-input lookup tables (LUTs) with parallel two-input AND gates receiving two of the four LUT input signals, associated registers, and a carry chain receiving one input signal from the AND gate output, a loadable up-down counter is formed by connecting the register output to one of the terminals serving as both a LUT input terminal and an AND gate input terminal. A load control signal is connected to another input terminal common to the LUT and the AND gate. Thus the AND gate disables the carry chain during loading of the counter and applies the count value to the carry chain during counting.