Column address decoder for two bit prefetch of semiconductor memory

Abstract

A column address decoder for two bit prefetch of a semiconductor device and a decoding method thereof are provided. The column address decoder includes a memory cell array having a plurality of memory cells for storing data and redundancy memory cells for replacing poor memory cells, a plurality of bit lines connected to the memory cells, a plurality of input and output lines, a plurality of switching means connected between the bit lines and the input and output lines. It also includes an even predecoder for receiving the less significant bits of the address received as input from the outside and predecoding the less significant bits in which the least significant bit is `0` of the less significant bits, an inverting decoder for reproducing the less significant bits of the external address corresponding to the address predecoded by the even predecoder, and a redundancy enable signal generating portion for generating a redundancy enable signal for receiving the output of the inverting decoder and activating one of the redundancy memory cells. According to the present invention, the data processing speed of the semiconductor memory device is increased.