The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2000
Filed:
Oct. 23, 1998
Applicant:
Inventors:
Jae-Goo Lee, Kyungki-Do, KR;
Young-Hyun Jun, Seoul, KR;
Assignee:
LG Semicon Co., Ltd., Cheongju, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
327276 ; 327277 ;
Abstract
A negative delay circuit (NDC) has an NDC array operated in a high frequency. The circuit varies a number of unit delay stages at an input stage of the NDC array according to a locking fail signal in a low frequency region. The NDC can carry out a negative delay operation in a wide band even when a number of the stages in the NDC array is small. The present invention decreases a size of a chip, and in addition, reduces an unnecessary current consumption by preventing a locking from re-occurring at a stage in a back portion because the NDC array has a delay value less than one clock.