The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2000
Filed:
Dec. 15, 1998
Oak Technology, Inc., Sunnyvale, CA (US);
Abstract
An apparatus and method for interfacing integrated circuits having incompatible input-output signal offset voltages that is relatively inexpensive and yet is also insensitive to noise. The apparatus of the present invention includes a receiver circuit for receiving differential signals on a differential line, comprising: (1) an interface circuit coupled to the differential signal line for removing a first offset voltage from the differential signal and biasing the differential signal to generate a biased differential signal having a second offset voltage, the interface circuit including a plurality of capacitive devices, (2) a differential amplifier circuit coupled to the interface circuit for converting the biased differential signal into a single-ended signal, (3) a Schmitt trigger circuit coupled to the differential amplifier circuit for filtering the single-ended signal to generate a filtered single-ended signal and (4) a latch circuit coupled to the Schmitt trigger circuit for filtering and asynchronously latching the filtered single-ended signal to generate a sustained, filtered digital signal. The method of the present invention comprises the steps of: (1) capacitively removing a first offset voltage from the differential signal, (2) biasing the differential signal to generate a biased differential signal having a second offset voltage, (3) converting the biased differential signal into a single-ended signal, (4) filtering the single-ended signal using a hysteresis-loop transfer function to generate a filtered single-ended signal and (5) filtering and latching the filtered single-ended signal using a delayed regenerative feedback, hysteresis-loop transfer function to generate a sustained, filtered digital signal.