The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2000

Filed:

Apr. 26, 1999
Applicant:
Inventors:

Gary G Fang, San Jose, CA (US);

David Castaneda, Sunnyvale, CA (US);

Chowdhury F Rahim, Saratoga, CA (US);

Assignee:

Maxim Integrated Products, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326126 ; 326 92 ;
Abstract

Buffers having an output pull-up transistor controlled by the input signal, an output pull-down transistor and a pull-down transistor control circuit. A current source provides a current that is divided between the pull-up transistor and the pull-down transistor control circuit to maintain the desired output voltage. A boost capacitor is coupled between the output and the pull-down transistor control circuit to provide good dynamic response to the circuit even in the presence of substantial capacitive loads on the output. In addition a second capacitor is coupled between the pull-down transistor control circuit and a fixed voltage to provide a low frequency pole internal to the circuit. The connection of the boost capacitor to the pull-down transistor control circuit and the connection of the second capacitor to the pull-down transistor control circuit are separated by a substantial resistance, allowing the effect of each capacitor to be substantially independent of each other. Exemplary circuits are disclosed incorporating these and other features.


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