The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2000

Filed:

May. 23, 1997
Applicant:
Inventor:

Kazuyuki Yahiro, Kawasaki, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438787 ; 438624 ; 438902 ;
Abstract

In a method of manufacturing a semiconductor device, a first plasma insulating film having a thickness of 0.1 .mu.m or more is formed on the semiconductor substrate with lower-surface wirings thereon. The semiconductor substrate is moved into a pressure-reduced CVD device, and then an SiH.sub.4 gas and H.sub.2 O.sub.2 are supplied into the pressure-reduced CVD device to react them to each other in a vacuum of 650 Pa or less within the temperature range of -10.degree. C. to +10.degree. C. to form a reflow SiO.sub.2 film having a thickness of 0.4 .mu.m to 1.4 .mu.m on the semiconductor substrate. The semiconductor substrate is put in a vacuum of 6.5 pascal for 30 seconds or more. Thereafter, the semiconductor substrate is put at a high temperature of 300.degree. C. to 450.degree. C. for 120 to 600 seconds. A second plasma insulating film having a thickness of 0.3 .mu.m or more and serving as a cap film is formed on the semiconductor substrate. The crack resistance of the reflow insulating film formed in the above steps is improved, and the flatness of the reflow insulating film is improved.


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