Method of making chip size package substrate

Abstract

A method of fabricating an electrically conductive via in a substrate which includes providing an electrically insulating substrate having first and second opposing surfaces and forming a first layer of electrically conductive material on the first of the opposing surfaces and forming a second layer of electrically conductive material on the second of the opposing surface. In accordance with one embodiment, the second layer has a thickness greater than the electrically insulating layer and no greater than the sum of the thicknesses of the electrically insulating layer and the first layer. In accordance with a second embodiment, the second layer has a thickness greater than the electrically insulating layer and no greater than the sum of the thicknesses of the electrically insulating layer and the first layer. A hole is formed in the first layer having sidewalls. A stud is formed in the second layer aligned with the hole in the first layer. The stud is forced through the substrate and into contact with the sidewalls of the hole. The stud preferably has a cross section to provide a friction fit with the sidewalls of the hole. In accordance with the second embodiment, the stud will extend beyond the bottom side of the polyimide layer to provide the effect of a ball from a ball grid array. The substrate can be heated to a thermoplastic state prior to forcing the stud through the substrate, if necessary. The substrate is preferably a polyimide and the electrically conductive material is preferably taken from the class consisting of copper and copper-based materials.