Digital signal processing circuitry having integrated timing information

Abstract

Digital signal processing circuitry implemented in ASICs or FPGAs is built by combining multi-component constructs (e.g. macrocells). These circuits may be modified to include a timing channel by augmenting selected ones of the constructs to include a path which propagates a timing signal with a delay that compensates for the signal processing delay through the construct. The selected constructs are those that are used in a critical processing path in the digital signal processing circuitry. A timing compensation circuit may also be defined as a construct. This block receives two digital data signals having accompanying timing signals and delays the first signal that provides valid data until the second signal also provides valid data, as determined by their timing signals. A configurable arithmetic and logic unit (ALU) made using these techniques includes a timing compensation circuit, a look-up table and an accumulator. The configurable ALU may also include a timing signal selection circuit which selects between the each of two input timing signals, the logical AND of the input timing signals and the logical OR of the two input timing signals to produce an output timing signal. A programmable multiply-accumulator includes a matrix of multipliers, each of which may receive one of a plurality of input signals. The input signals are delayed through a pipeline and a portion of this pipeline is reserved for delaying one or more timing signals associated with the plurality of input signals. The delayed timing signals form the timing signals that are associated with the output signal of the programmable multiply accumulator.