The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2000
Filed:
Mar. 12, 1999
Applicant:
Inventor:
Takehiko Shimomura, Tokyo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L / ; H03L / ; H03L / ;
U.S. Cl.
CPC ...
331-2 ; 331 45 ;
Abstract
A PLL circuit including multiple sets of phase locked loops, each of which has a phase comparator, a charge pump, a low pass filter, as oscillator, a clock generator and a frequency divider. The various oscillators of the multiple sets each have a different oscillation frequency. The clock generator generates a multiphase clock signal from a single phase clock signal generated by the oscillator. The PLL circuit generates multiple single phase clock signals and multiphase clock signals without need to tune the oscillation frequency of the VCOs over a wide range. The noise of the PLL is reduced since each VCO covers a smaller range of oscillation frequencies.