The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2000

Filed:

Jul. 22, 1999
Applicant:
Inventor:

Vadim V Ivanov, Tucson, AZ (US);

Assignee:

Burr-Brown Corporation, Tucson, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F / ;
U.S. Cl.
CPC ...
330253 ; 330255 ;
Abstract

A differential amplifier includes a rail-to-rail input stage including differentially coupled first (13) and second (14) P-channel input transistors, and differentially coupled third (17) and fourth (18) N-channel input transistors. The drains of the first and second input transistors are coupled to a first folded cascode circuit which includes first (25) and second (26) P-channel cascode transistors. The drains of the third and fourth input transistors are coupled to a second folded cascode circuit which includes third (36) and fourth (37) N-channel cascode transistors. An output stage includes a P-channel pull-up transistor and an N-channel pull-down transistor and a class AB bias circuit coupled between the gates thereof. The gates of the first (25) and third (36) cascode transistors are coupled to first and second reference voltages, respectively. A first gain boost circuit (58) amplifies signals on the drains of first and second input transistors to produce a bias signal on the gate of the second cascode transistor (26) coupled to the gate of the pull-up transistor. A second gain boost circuit (57) amplifies signals on the drains of third and fourth input transistors to produce a bias signal on the gate of the fourth cascode transistor (37) coupled to the gate of the pull-down transistor.


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